Hackers can now steal data from faraday cage air-gapped computers.
https://thehackernews.com/2018/02/airgap-computer-hacking.html
- Techniques: Magneto and ODINI
- Malware generates a pattern of magnetic field frequencies by overloading the CPU with calculations that increase power consumption and generate a stronger magnetic field
- The malware leaves only a small footprint in the memory.
- At the OS level the program requires no special privileges, works in user space (busy loops, mainly)
- MAGNETO is a short-distance attack, where an android app installed on the attacker’s smartphone can receive stolen data with the help of phone’s magnetometer (magnetic sensor)
- ODINI - slightly longer range using a dedicated magnetic sensor.
| Work |
Signal generation |
Receiver |
Max bitrate |
Max distance |
| ODINI |
CPU |
Magnetic sensor |
40 bit/sec |
100 to 150cm |
| MAGNETO |
CPU |
Smartphone |
5-0.2 bit/sec |
0 to 12cm |
| Hard Disk Drive |
HDD |
Smartphone |
2-0.06 bit/sec |
0 to 12cm |
Open Hardware Ecosystem with RISC-V
https://fosdem.org/2018/schedule/event/riscv/
- RISC-V - free and open ISA standard
- ISA = Instruction Set Architecture
- RISC-V binutils, GCC, Linux and glib have been released by upstream as of Feb 1, 2018
- In 2010 - time to choose an ISA for next set of projects. Obvious choices: x86 and ARM
- X86 impossible - IP issues, too complex
- ARM mostly impossible - no 64-bit, IP issues, complex
- They started 3-month project, in summer 2010 to develop their own clean-slate ISA
- In 2014 they released the frozen base user spec (first release in may 2011)
- RISC-V is the smallest ISA for 32- and 64-bit addresses
- Current state:
- User Mode ISA specification:
- ALU, branches, memory
- M extension for multiplication
- A extension for atomics
- F and D extensions for single and double precision floating point
- C extension for compressed instructions (16-bit)
- Privileged Mode ISA specification:
- Supervisor mode
- Hypervisor mode
- Machine mode
- External Debug specification
- Debug machine-mode software over JTAG
- Future of RISC-V
- Debian, Fedore - bootstrap is in progress
- V extension for vectors
- J extension for JITs (primary target - is advanced JVMs)
- HiFive Unleashed: Multi-Core RISC-V Linux Development Board
- 4+1 Multi-Core Coherent Configuration, up to 1.5GHz
- 1x Gigabit Ethernet
- 8GB 64-bit DDR4 with ECC
- MicroSD card for removable storage